1. Field of the Invention
The present invention relates to a carry propagation circuit of a parallel-type full adder. More particularly, it relates to a constitution of a circuit for propagating a carry signal at high speed from a lower bit to a higher bit in a parallel-type full adder having a plurality of bits and constituted by digital logic circuits.
2. Description of the Related Art
With recent developments in large scale integration (LSI) technology, demand has been increasing for high-level integration of a multi-bit (32 bits or more) parallel-type full adder for realization of high-speed processing. To cope with this, various approaches to provide a bypath or bypaths in a carry propagation circuit, and thus to constitute a high speed adder, have been proposed. As an example of the approaches, a so-called Manchester-type carry propagation circuit is known in which a plurality of transfer or transmission gates (TGs) are serially connected in multiple stages to constitute a Manchester carry chain and a number of bypaths are appropriately arranged in the Manchester carry chain. The Manchester-type carry propagate circuit has an advantage of realizing a high speed operation with a small number of elements, compared with other approaches.
Even in this approach, however, there are several drawbacks to be improved as described later in detail. For example, as the number of bits to be simultaneously processed is increased, a signal propagation delay becomes significant, and accordingly, room for improvement still remains. Thus, a novel approach for the arrangement of bypaths is desired which enables increased, high speed operation.